Semiconductor device having merged epitaxial pattern and method for fabricating the same

A semiconductor device comprising:

• a substrate;
• a first active pattern disposed on the substrate and extending in a first direction;
• a second active pattern stacked on the first active pattern and extending in the first direction;
• a gate structure disposed on the substrate and extending in a second direction intersecting the first direction, each of the first active pattern and the second active pattern passing through the gate structure;
• a first epitaxial pattern disposed on a side surface of the gate structure, and connected to the first active pattern;
• a second epitaxial pattern disposed on the side surface of the gate structure and connected to the second active pattern;
• an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern;
• and
• a semiconductor film interposed between the insulating pattern and the second epitaxial pattern,
• wherein the second epitaxial pattern includes an epitaxial layer grown using the second active pattern and the semiconductor film as seed layers, and
• wherein a top surface of the first epitaxial pattern has a contact recess recessed toward the substrate.

A semiconductor device comprising:

• a substrate;
• a plurality of lower sheet patterns sequentially stacked on the substrate, and spaced apart from each other, wherein each of the plurality of lower sheet patterns extends in a first direction;
• a plurality of upper sheet patterns sequentially stacked on the plurality of lower sheet patterns, and spaced apart from each other, wherein each of the plurality of upper sheet patterns extends in the first direction;
• an isolation pattern interposed between the plurality of lower sheet patterns and the plurality of upper sheet patterns;
• a gate structure disposed on the substrate and extending in a second direction intersecting the first direction, wherein each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns pass through the gate structure;
• a first epitaxial pattern disposed on a side surface of the gate structure, and connected to the plurality of lower sheet patterns, wherein the first epitaxial pattern has a first conductivity type;
• a second epitaxial pattern disposed on the side surface of the gate structure, and connected to the plurality of upper sheet patterns, wherein the second epitaxial pattern has a second conductivity type different from the first conductivity type;
• an insulating pattern disposed on a side surface of the isolation pattern and interposed between the first epitaxial pattern and the second epitaxial pattern;
• and
• a polysilicon film disposed between the insulating pattern and the second epitaxial pattern and extending along a top surface of the insulating pattern,
• wherein a top surface of the first epitaxial pattern has a contact recess recessed toward the substrate.