Gate structure for semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHuan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Ching
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Abstract
The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.
Claims20
A method, comprising:
- forming, on a substrate, a vertical structure comprising first and second nanostructured layers;
- depositing a semiconductor layer on sidewalls of the vertical structure;
- forming, on the substrate, an isolation structure adjacent to the vertical structure;
- forming a sacrificial gate structure on the vertical structure and the isolation structure;
- removing the semiconductor layer, the second nanostructured layer, and the sacrificial gate structure to form a recess;
- forming a gate dielectric layer in the recess, comprising:
- forming a first portion of the gate dielectric layer in a lower portion of the recess;
- and
- forming a second portion of the gate dielectric layer in an upper portion of the recess;
- and
- forming a gate electrode on the first portion of the gate dielectric layer, wherein a top surface of the gate electrode is below a top surface of the gate dielectric layer.
A method, comprising:
- forming, on a semiconductor substrate, vertical structures having sacrificial layers and channel regions comprising one or more doped semiconductor materials;
- depositing semiconductor layers on sidewalls of the vertical structures;
- forming isolation structures between the vertical structures;
- forming a sacrificial gate structure on top surfaces of the vertical structures and the isolation structures and on sidewalls of the semiconductor layers;
- forming opposing gate spacers adjacent to the sacrificial gate structure;
- removing the semiconductor layer, the sacrificial layers, and the sacrificial gate structure;
- forming a gate dielectric layer on the isolation structures and the channel regions;
- and
- forming a gate metal stack on the gate dielectric layer, wherein the gate dielectric layer and the opposing gate spacers extend above a top surface of the gate metal stack.
A method, comprising:
- forming, on a substrate, a first vertical structure, the first vertical structure comprising a channel region and a sacrificial layer;
- depositing semiconductor layers on sidewalls of the first vertical structure;
- forming, on the substrate, a second vertical structure over the substrate and on sidewalls of the semiconductor layer, the second vertical structure comprising a dielectric stack;
- forming a sacrificial gate structure over the channel region of the first vertical structure;
- forming two opposing spacers along sidewalls of the sacrificial gate structure;
- forming a first dielectric layer over side surfaces of the two opposing spacers, the first dielectric layer comprising two opposing side surfaces and top surfaces substantially coplanar with top surfaces of the two opposing spacers;
- removing the sacrificial layer, the semiconductor layers, and the sacrificial gate structure;
- and
- forming a gate metal stack between the two opposing side surfaces of the first dielectric layer, wherein a top surface of the gate metal stack is below the top surfaces of the first dielectric layer.
Dependencies are inferred from the claim text.