Silicon super junction structures for increased voltage

A super junction device comprising:

• a silicon substrate forming a drain region for the device;
• a gate region;
• a source region;
• an N-type region extending from the silicon substrate up to the gate region;
• and
• a P-type region extending from the silicon substrate up to the source region, wherein the device has a breakdown voltage of greater than or about 1000 V, and a doping concentration of the P-type region is greater than about 8 times the doping concentration of the N-type region.

A method of forming a super junction device, the method comprising:

• forming a first N-type material on a substrate, wherein the first N-type material has a height of greater than or about 70 μm above the substrate;
• etching a trench in the first N-type material, wherein the trench extends from a top surface of the first N-type material down to at least a top surface of the substrate to form a first N-type region;
• forming a P-type liner on a sidewall portion of the first N-type region in the trench, wherein the P-type liner is less than or about 300 nm;
• filling the trench with an N-type material to form a second N-type region such that the P-type liner is between the first N-type region and the second N-type region.