Ultra-steep slope and high-performance strain effect transistor

A transistor, comprising:

• a substrate;
• a gate formed in or on a surface of the substrate, the gate comprising a piezoelectric material;
• a drain and a source, each of the drain and the source formed in or on a surface of the gate;
• a channel formed in or on a surface of the gate, the channel located between the drain and the source, the channel comprising a semiconducting/semi-metallic material;
• a source contact region comprising a transistor layer stack in which a source contact is vertically aligned with the source, the channel, and the gate, the source contact being formed at the source and configured to anchor the semiconducting/semi-metallic material to the piezoelectric material via mechanical or chemical adhesion between the semiconducting/semi-metallic material and the piezoelectric material;
• a drain contact region comprising a transistor layer stack in which a drain contact is vertically aligned with the drain, the channel, and the gate, the drain contact being formed at the drain and configured to anchor the semiconducting/semi-metallic material to the piezoelectric material via mechanical or chemical adhesion between the semiconducting/semi-metallic material and the piezoelectric material;
• wherein strain induced transduction in the gate causes contact modification between the channel and the source contact and between the channel and the drain contact;
• wherein such that strain transduction is limited to the channel material within the source contact region and the drain contact region due to:
• the anchoring by the source contact and drain contact;
• and tensile strength of the source contact material and the drain contact material.