Semiconductor device with floating main body region vertically separting source from drain and method of forming the same
AssigneeWinbond Electronics Corp.
InventorsYu-Ting Chen, Kai Jen
Life of this patent
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Abstract
A semiconductor device includes: a substrate; a source region disposed on the substrate; a drain region disposed on the source region; and a floating main body region disposed between the source region and the drain region. The floating main body region vertically separates the source region from the drain region. The semiconductor device further includes: a gate region laterally wrapped around the floating main body region; and a gate dielectric located between the floating main body region and the gate region, and insulated the floating main body region from the gate region. A material of the gate dielectric has a negative capacitance feature.
Claims15
A semiconductor device, comprising:
- a substrate;
- a source region disposed on the substrate;
- a drain region disposed on the source region;
- a floating main body region disposed between the source region and the drain region, wherein the floating main body region vertically separates the source region from the drain region;
- a gate region laterally wrapped around the floating main body region, wherein the gate region wraps around a portion of the source region and a portion of the drain region;
- and
- a gate dielectric located between the floating main body region and the gate region, and insulated the floating main body region from the gate region, wherein a material of the gate dielectric has a negative capacitance (NC) feature,
- wherein the gate dielectric comprises an air gap in contact with the drain region, wherein, from the perspective of the floating main body region, a portion of the gate dielectric close to the source region and a portion of the gate dielectric close to the drain region appear to be an asymmetrical configuration.
A method of forming a semiconductor device, comprising:
- providing a substrate;
- sequentially forming a source region, a floating main body region, and a drain region on the substrate by sequentially depositing a source layer, a floating main body layer, and a drain layer on the substrate, followed by patterning the drain layer, the floating main body layer, and a portion of the source layer, wherein a portion of the source layer not patterned becomes a source line electrically connected to the source region;
- forming a gate region wrapping around the floating main body region, wherein the gate region wraps around a portion of the source region and a portion of the drain region;
- and
- forming a gate dielectric wrapping around the floating main body region before forming the gate region, wherein a material of the gate dielectric has a negative capacitance feature,
- wherein the gate dielectric layer and the gate layer are conformally deposited on an exposed surface of the source line, on sidewalls of the source region and the floating main body region, and on a sidewall and a top surface of the drain region, followed by etching back the gate dielectric layer and the gate layer.
Dependencies are inferred from the claim text.