FinFET isolation structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
Life of this patent
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Abstract
A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeOx, SiGe, SiP or SiPOx, where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.
Claims20
A device, comprising:
- a semiconductive substrate;
- a stop layer over the semiconductive substrate and comprising SiGeOx, SiGe, SiP or SiPOx, where x is greater than 0;
- a semiconductive fin over the stop layer;
- a fin isolation structure connected to a sidewall of the semiconductive fin;
- and
- a source/drain epitaxial layer adjacent to the semiconductive fin, wherein the semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure, and the source/drain epitaxial layer is separated from the semiconductive substrate by the stop layer.
A device, comprising:
- a semiconductive substrate;
- a semiconductive fin over the semiconductive substrate;
- a stop layer between the semiconductive fin and the semiconductive substrate;
- a source/drain epitaxial layer connected to the semiconductive fin;
- and
- a fin isolation structure over the semiconductive substrate and comprising:
- a top portion having a first linear sidewall;
- and
- a bottom portion having a second linear sidewall inclined to the first linear sidewall of the top portion, wherein an interface between the top portion and the bottom portion of the fin isolation structure is lower than a top surface of the source/drain epitaxial layer.
A device, comprising:
- a semiconductive substrate;
- a fin isolation structure over the semiconductive substrate;
- a stop layer over the semiconductive substrate and in contact with a sidewall of the fin isolation structure;
- a semiconductive fin over the stop layer and in contact with the sidewall of the fin isolation structure;
- and
- a gate spacer over the semiconductive fin and in contact with the sidewall of the fin isolation structure.
Dependencies are inferred from the claim text.