Semiconductor memory device, method for fabricating the same and electronic system including the same

A semiconductor memory device comprising:

• a cell substrate;
• a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate;
• a channel structure extending in a vertical direction, intersecting an upper side of the cell substrate, and penetrating the mold structure;
• and
• a bit line on the mold structure,
• wherein the channel structure includes a ferroelectric layer, an n-type channel layer, a p-type channel layer, and a core insulating layer that are sequentially stacked on side surfaces of each of the plurality of gate electrodes,
• each of the n-type channel layer and the p-type channel layer electrically connect the cell substrate and the bit line, and
• the n-type channel layer includes a first oxide layer, and a second oxide layer, and an interfacial layer, the first oxide layer and the second oxide layer being sequentially stacked on the ferroelectric layer, the interfacial layer including an oxygen vacancy and between the first oxide layer and the second oxide layer.

An electronic system comprising:

• a main board;
• a semiconductor memory device on the main board;
• and
• a controller electrically connected to the semiconductor memory device, on the main board,
• wherein the semiconductor memory device includes,
• a cell substrate,
• a plurality of gate electrodes sequentially stacked on the cell substrate,
• a semiconductor layer extending in a vertical direction, intersecting an upper side of the cell substrate, intersecting the plurality of gate electrodes, and
• a gate dielectric layer including ferroelectrics, between each of the gate electrodes and the semiconductor layer,
• wherein the semiconductor layer includes an n-type channel layer and a p-type channel layer each extending in the vertical direction, and
• the n-type channel layer includes an oxide 2-dimensional electron gas (oxide 2-DEG) layer extending in the vertical direction.