Semiconductor structure and method for forming the same

A semiconductor structure, comprising:

• a substrate;
• a first vertical stack comprising first nanostructures, wherein the first nanostructures are suspended over the substrate;
• a first source/drain feature and a second source/drain feature, attached to opposite sides of the first nanostructures;
• a first gate structure, wrapping around each of the first nanostructures, wherein the first gate structure comprises a first gate dielectric layer and a first gate electrode formed on the first gate dielectric layer;
• and
• first inner spacers and second inner spacers, formed on opposite sides of the first gate structure and between the first nanostructures, wherein the first inner spacers and the second inner spacers are connected to the first source/drain feature and the second source/drain feature, respectively,
• wherein the first gate dielectric layer comprises a first portion formed on the first nanostructures, a second portion formed on sidewalls of the first inner spacers, and a third portion formed on sidewalls of the second inner spacers, and
• wherein a second thickness of the second portion and a third thickness of the third portion are smaller than a first thickness of the first portion.

A semiconductor structure, comprising:

• a plurality of nanostructures, arranged over a base portion in a vertical direction;
• an isolation structure, disposed around the base portion;
• a gate structure, comprising interfacial layers wrapped around each of the nanostructures, a gate dielectric layer over the interfacial layers, and a gate electrode layer over the gate dielectric layer, wherein the gate dielectric layer comprises horizontal portions formed on the interfacial layers and vertical portions extending from the horizontal portions;
• source/drain features, disposed on opposite sides of the gate structure in a first direction and attached to the nanostructures, wherein the first direction is different from the vertical direction;
• and
• inner spacers, formed on the opposite sides of the gate structure in the first direction and between the nanostructures in the vertical direction, wherein the inner spacers space apart the nanostructures and the source/drain features,
• wherein a first thickness of the horizontal portions of the gate dielectric layer in the vertical direction is different from a second thickness of the vertical portions of the gate dielectric layer in the first direction,
• wherein each of the nanostructures comprises terminal portions connected to the source/drain features and a middle portion extending between the terminal portions, and wherein third thicknesses of the terminal portions are greater than a fourth thickness of the middle portion,
• wherein the inner spacers are disposed between the terminal portions in the vertical direction, and
• wherein in a cross-sectional view, the horizontal portions extend on bottom surfaces or top surfaces of the middle portions, and the vertical portions extend on sidewalls of the terminal portions.