Semiconductor device having nanostructure transistor and methods of fabrication thereof

A method for forming a semiconductor device structure, comprising:

• forming a fin structure on a substrate, the fin structure comprising first semiconductor layers and second semiconductor layers alternatingly stacked;
• forming a sacrificial gate structure over a portion of the fin structure;
• removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure;
• removing edge portions of the second semiconductor layers;
• subjecting the first semiconductor layers and the substrate to a plasma treatment to selectively form a passivation layer on sidewalls of the first semiconductor layers;
• forming dielectric spacers on sidewalls of the second semiconductor layers and in between adjacent first semiconductor layers;
• forming an epitaxial source/drain feature in the source/drain region;
• removing portions of the sacrificial gate structure to expose the first and second semiconductor layers;
• removing the second semiconductor layers;
• forming a gate dielectric layer to surround an exposed surface of each first semiconductor layer;
• and
• forming a gate electrode layer on the gate dielectric layer.

A method for forming a semiconductor device structure, comprising:

• forming a first source/drain epitaxial feature over a substrate;
• forming a second source/drain epitaxial feature formed over the substrate;
• forming two or more semiconductor layers between the first source/drain epitaxial feature and the second source/drain epitaxial feature, wherein each of the two or more semiconductor layers has a surface portion comprising a halogen;
• forming a gate dielectric layer to surround a portion of one of the two or more semiconductor layers;
• forming a gate electrode layer on the gate dielectric layer;
• and
• forming a dielectric spacer between the semiconductor layers, wherein the dielectric spacer comprises:
• a first surface in contact with the gate dielectric layer;
• and
• a second surface adjacent the first source/drain epitaxial feature, the second surface having a curved profile.