Memory device

A memory device, comprising:

• a substrate;
• a memory cell array disposed on the substrate and including a plurality of memory cells, wherein each of the plurality of memory cells includes:
• a transistor unit, wherein the transistor unit includes a source region, a drain region, and a gate structure;
• and
• a memory unit electrically connected to the transistor unit;
• and
• a memory cell interconnection structure disposed on the substrate, wherein the memory cell interconnection structure is configured to establish an electrical connection between the plurality of memory cells, and the memory cell interconnection structure includes:
• a dielectric layer directly covering the substrate and the transistor units;
• and
• a plurality of source lines disposed on the substrate and extending along a first direction, wherein each of the plurality of source lines is embedded in the dielectric layer and comes in contact with the source region of a corresponding one of the transistor units;
• wherein the substrate further includes a plurality of isolation structures formed in the substrate, and each of the plurality of isolation structures extends along the second direction and intersects with the plurality of source lines, so as to separate any two of the transistor units that are arranged along the first direction and adjacent to each other;
• wherein each of the plurality of isolation structures has a plurality of insulation portions that respectively overlap with the plurality of source lines, a surface of each of the plurality of insulation portions has a recess, a part of each of the plurality of source lines is filled into the recess of a corresponding one of the plurality of insulation portions and directly contacts the corresponding insulation portion, and a depth of each of the recesses is greater than a depth of the source region in the substrate.