Memory array having air gaps
AssigneeMicron Technology, Inc.
InventorsPaolo Fantini, Paolo Tessariol, Enrico Varesi, Lorenzo Fratin
Life of this patent
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Abstract
Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
Claims20
An apparatus, comprising:
- processing circuitry associated with one or more memory devices and configured to cause the apparatus to:
- select, for an operation, a memory cell in a three-dimensional memory array that comprises a plurality of chalcogenide memory cells, a plurality of first word lines, a plurality of second word lines, and a plurality of pillars, wherein the plurality of first word lines are separated from one another by one or more first voids, and wherein the plurality of second word lines are separated from one another by one or more second voids;
- and
- apply, based at least in part on selecting the memory cell, a first voltage to a word line of the plurality of first word lines and a second voltage to a pillar of the plurality of pillars, the word line and the pillar being for accessing the memory cell.
A method, comprising:
- selecting, for an operation, a memory cell in a three-dimensional memory array that comprises a plurality of chalcogenide memory cells, a plurality of first word lines, a plurality of second word lines, and a plurality of pillars, wherein the plurality of first word lines are separated from one another by one or more first voids, and wherein the plurality of second word lines are separated from one another by one or more second voids;
- and
- applying, based at least in part on selecting the memory cell, a first voltage to a word line of the plurality of first word lines and a second voltage to a pillar of the plurality of pillars, the word line and the pillar being for accessing the memory cell.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
- select, for an operation, a memory cell in a three-dimensional memory array that comprises a plurality of chalcogenide memory cells, a plurality of first word lines, a plurality of second word lines, and a plurality of pillars, wherein the plurality of first word lines are separated from one another by one or more first voids, and wherein the plurality of second word lines are separated from one another by one or more second voids;
- and
- apply, based at least in part on selecting the memory cell, a first voltage to a word line of the plurality of first word lines and a second voltage to a pillar of the plurality of pillars, the word line and the pillar being for accessing the memory cell.
Dependencies are inferred from the claim text.