Memory circuitry and method used in forming memory circuitry

A method used in forming memory circuitry, comprising:

• forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction;
• forming a stair-step structure in the stair-step region, the stair-step structure comprising a first flight of stairs extending along a first direction and a second flight of stairs extending along the first direction and opposing the first flight of stairs, each stair of the first and second flights of stairs comprising at least two of the first tiers and at least two of the second tiers, the first and second flights of stairs being separated by a cavity;
• forming a spacer-forming layer within the cavity;
• anisotropically etching the spacer-forming material to form first and second spacers that extend along the first direction directly above the first flight of stairs, the first and second spacers being spaced from one another in a second direction that is orthogonal to the first direction;
• and
• using the first and second spacers as a mask while etching there-between through one of the first tiers and one of the second tiers within one individual of the stairs to form two higher-depth treads having a lower-depth tread there-between in the individual stairs along the second direction, the two higher-depth treads and the lower-depth tread individually comprising conducting material of individual of the first tiers in the finished-circuitry construction.