Stacked memory structure with dual-channel transistor

A 3D memory structure comprising:

• a plurality of tiers arranged in a vertical stack, individual tiers including an array of 1T-1C memory cells, an individual 1T-1C memory cell including
• a wordline conductor extending horizontally,
• a bitline conductor extending vertically,
• a spacer comprising an electrically insulating material, the spacer being between a first side of the wordline conductor and the bitline conductor, the spacer being directly on the first side of the wordline conductor,
• a semiconductor material having first and second horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and having a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions,
• a high-κ dielectric between the semiconductor material and the wordline conductor, the high-κ dielectric being separate from the spacer and around the spacer, the high-κ dielectric being directly on the second side of the wordline conductor,
• and
• a capacitor having a first conductor, a second conductor, and an insulator between the first conductor and the second conductor, wherein the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

A 3D memory structure comprising:

• a plurality of tiers stacked vertically, individual tiers containing an array of memory cells, individual memory cells including one transistor structure and one capacitor;
• wordline conductors in each tier extending horizontally along a first horizontal axis and spaced along a second horizontal axis, wherein wordline conductors in the plurality of tiers are arranged spaced-apart in vertical stacks;
• a plurality of bitline conductors extending vertically, bitline conductors positioned between adjacent vertical stacks of wordline conductors, and spaced apart along the first horizontal axis;
• a plurality of transistors spaced apart along individual wordline conductors, individual transistors having a spacer comprising an electrically insulating material, the spacer being between a first side of the wordline conductor and one of the plurality of bitline conductors and the spacer being directly on the first side of the wordline conductor, a dielectric and a semiconductor material extending along a top, a second side, and a bottom of one of the plurality of wordline conductors and the semiconductor material extending along a top and bottom of the spacer to the one of the plurality of bitline conductors, wherein the dielectric is between the semiconductor material and the wordline conductor, and wherein the dielectric is separate from the spacer and is around the spacer, and wherein the dielectric is directly on the second side of the wordline conductor;
• a capacitor laterally adjacent the transistor in an individual memory cell, the capacitor comprising a first conductor abutting the semiconductor material of the transistor, and a second conductor spaced from the first conductor by an insulator between the first and second conductors;
• and
• ground terminals electrically connecting the second conductor of a plurality of capacitors arranged in a vertical stack.