Receivers using power saving and partial decision feedback equalization methods

A receiver comprising:

• a data line configured to receive a data symbol having multiple voltage levels, the data symbol being modulated according to pulse-amplitude modulation (PAM) and encoded according to maximum transition avoidance (MTA) coding that prevents a maximum transition (MT) event from occurring between symbols;
• a partial decision feedback equalization (DFE) circuit including switches connected to the data line, the partial DFE circuit being configured to selectively equalize the data symbol, based on a previous data symbol value;
• a slicer circuit connected to the data line and configured to determine a voltage level of the selectively equalized data symbol;
• a decoder configured to decode the data symbol, based on multiple decision values of the slicer circuit;
• and
• a control circuit configured to store the multiple decision values as the previous data symbol value and provide the previous data symbol value to the partial DFE circuit,
• wherein the control circuit is further configured to selectively turn on or off the switches of the partial DFE circuit according to the previous data symbol value.

A method comprising:

• receiving a data symbol having multiple voltage levels through a data line, the data symbol being modulated according to pulse-amplitude modulation (PAM) and encoded according to maximum transition avoidance (MTA) coding that prevents a maximum transition (MT) event from occurring between symbols, and the multiple voltage levels including a highest level and a lowest level;
• selectively equalizing the data symbol, based on a previous data symbol value, by using a partial decision feedback equalization (DFE) circuit;
• comparing the equalized data symbol with middle reference voltage levels by using multiple comparator circuits;
• providing multiple decision values as a result of the comparison;
• decoding the data symbol, based on the multiple decision values;
• storing the multiple decision values as the previous data symbol value;
• and,
• when the previous data symbol value corresponds to the lowest level, disabling a comparator circuit that decides the highest level, from among the multiple comparator circuits.