Transconductor with adaptive bias offset cancellation

A timing circuit comprising:

• a transconductor circuit that is configured to generate a tuning signal based on at least one error signal corresponding to a phase difference between a reference signal and an output signal of a voltage-controlled oscillator, the tuning signal being configured to tune the voltage-controlled oscillator;
• and
• an adaptive bias circuit that is configured to:
• generate a nulling signal based on an offset in the tuning signal created by the transconductor circuit;
• and
• provide the nulling signal to the transconductor circuit, the transconductor circuit being configured to adjust the tuning signal based on the nulling signal.

A semiconductor device comprising a phase lock loop of a timing circuit, the phase lock loop comprising:

• a voltage-controlled oscillator that is configured to generate an output signal of the phase lock loop;
• and
• a sub-sampling phase lock loop, the sub-sampling phase lock loop comprising:
• a radio frequency sampler circuit that is configured to obtain the output signal of the voltage-controlled oscillator and a reference signal and to generate a pair of error signals corresponding to a phase difference between the output signal and the reference signal;
• a transconductor circuit comprising:
• a gain stage that is configured to generate a gain signal based on the pair of error signals;
• a current mirror that is configured to generate a mirrored signal;
• and
• an output stage that is configured to generate a tuning signal based on the mirrored signal and the reference signal, the voltage-controlled oscillator being configured to generate the output signal based on the tuning signal;
• and
• an adaptive bias circuit comprising:
• a replica output stage, the replica output stage being configured to generate a replica signal based on the mirrored signal;
• a gain stage that is configured to generate an offset signal based on the tuning signal and the replica signal;
• a low pass filter that is configured to generate a filtered signal based on the offset signal;
• and
• an output stage that is configured to generate a nulling signal based on the filtered signal, the current mirror being configured to generate the mirrored signal based on a current of the nulling signal and a current of the gain signal.