Receiver circuit scheme capable of avoiding clock harmonic interferences and reducing phase errors to maintain demodulator capability

A receiver circuit comprising:

• a mixer for mixing a radio frequency signal with a local oscillator signal to generate an intermediate frequency signal;
• an intermediate frequency processing circuit, coupled to the mixer, for generating a baseband signal according to the intermediate frequency signal;
• and
• a receiver analog-to-digital converter (ADC), coupled to the intermediate frequency processing circuit, for sampling information of the baseband signal to convert the baseband signal into a digital reception signal according to a working sample rate;
• wherein the working sample rate is dynamically switched between a first sample rate and a second sample rate which are adjacent to a target sample rate, to make a harmonic of the first sample rate be not in a specific channel frequency of the radio frequency signal and a harmonic of the second sample rate be not in the specific channel frequency of the radio frequency signal;
• and the first sample rate is lower than the target sample rate while the second sample rate is higher than the target sample rate.