Clock synthesizer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWei Shuo Lin
Life of this patent
Estimating the term…
Abstract
A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.
Claims20
A clock synthesizer comprising:
- a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, wherein the DCCPI circuit is configured to:
- receive an input clock signal, and
- provide an output clock signal as an output from the input signal;
- a replica circuit connected to an output of the DCCPI circuit, wherein the replica circuit is operative to replicate the output clock signal and provide a replica clock signal;
- a phase detection circuit connected to the replica circuit, wherein the phase detection circuit is operative to:
- compare the replica clock signal with a reference clock signal, and
- provide, to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal;
- and
- wherein the DCCPI circuit is operative to:
- adjust a duty cycle of the input clock signal,
- interpolate a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, wherein the DCCPI circuit being operative to interpolate the phase value comprises the DCCPI circuit being operative to shift a rising edge of the input clock signal, and
- provide duty adjusted and phase interpolated input signal as the output clock signal.
A clock synthesizer comprising:
- a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, wherein the DCCPI circuit is configured to:
- receive an input clock signal,
- perform phase interpolation on the input clock signal,
- adjust a duty cycle of the input clock signal based on a difference between an average Direct Current (DC) voltage value of the clock signal and an average DC voltage value of an inverted clock signal, and
- provide an output clock signal as an output after adjusting the duty cycle;
- a replica circuit connected to the DCCPI circuit, wherein the replica circuit is operative to replicate the output clock signal and provide a replica clock signal;
- a phase detection circuit connected to the replica circuit, wherein the phase detection circuit is operative to:
- compare the replica clock signal with a reference clock signal, and
- provide, to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal;
- and wherein the DCCPI circuit is operative to:
- interpolate a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, and
- provide duty adjusted and phase interpolated input signal as the output clock signal.
A method of synthesizing a clock signal, the method comprising:
- replicating, by a replica circuit connected to an output of a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, an output clock signal of DCCPI circuit;
- comparing, by a phase detection circuit connected to the replica circuit, the replica clock signal with a reference clock signal;
- providing, by the phase detection circuit to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal;
- adjusting, by the DCCPI circuit, a duty cycle of the input clock signal;
- interpolating, by the DCCPI circuit, a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, wherein interpolating the phase value comprises shifting a rising edge of the input clock signal;
- and
- providing, by the DCCPI circuit, duty adjusted and phase interpolated input signal as the output clock signal.
Dependencies are inferred from the claim text.