Power allocation using multiple voltage domains for programmable logic devices
AssigneeAltera Corporation
InventorsMahesh K. Kumashikar, Ankireddy Nalamalpu, Md Altaf Hossain, Atul Maheshwari, Yuet Li, Mahesh A. Iyer
Life of this patent
Estimating the term…
Abstract
An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.
Claims20
An integrated circuit system comprising:
- programmable logic circuitry comprising:
- a first region of a plurality of regions comprising a first portion of routing resources of the programmable logic circuitry and configurable to operate at a first voltage;
- a second region of the plurality of regions comprising a second portion of the routing resources of the programmable logic circuitry and configurable to operate at a second voltage, and wherein the second voltage is higher than the first voltage, and wherein the programmable logic circuitry is programmed using voltage-aware placement and routing that assigns a critical path to the second region;
- and
- a plurality of level shifters configurable to enable independent voltage domains between the first region operating at the first voltage and the second region operating at the second voltage.
A system comprising:
- a programmable logic device configurable to operate:
- a first region at a first voltage, wherein the first region comprises a first portion of routing resources of programmable logic circuitry of the programmable logic device;
- and
- a second region at a second voltage higher than the first voltage, wherein the second region comprises a second portion of the routing resources of the programmable logic circuitry of the programmable logic device;
- and
- memory that stores instructions and a processor to implement the instructions, wherein the instructions cause the processor to:
- receive a system design for the programmable logic device;
- generate a bitstream to program the programmable logic device using voltage-aware placement and routing that assigns a critical path to the second region;
- and
- provide the bitstream to the programmable logic device to program the first region and the second region.
A method comprising:
- receiving, via a processor, a register-transfer level design comprising user-defined timing constraints;
- determining, via the processor, voltage-aware placement and routing based on the timing constraints;
- and
- based on the determination of the voltage-aware placement and routing:
- assigning to a first region of a plurality of regions of programmable logic circuitry, wherein the first region comprises a first portion of interconnection resources of the programmable logic circuitry, a lower voltage than a second region of the plurality of regions of programmable logic circuitry, wherein the second region comprises a second portion of the interconnection resources of the programmable logic circuitry;
- and
- generating a bit-stream to program the programmable logic circuitry using the voltage-aware placement and routing that assigns a critical path to the second region.
Dependencies are inferred from the claim text.