Charge transfer device having a bulged portion for clock frequencies from 100 MHz

A charge transfer device

• having a charge transfer channel in a semiconductor substrate
• having a doped conduction layer
• for movably accepting the charge carriers,
• having a sequence of at least two electrically isolated gates
• which adjacently succeed one another
• for transferring the charge carriers in the conduction layer in a flow direction,
• wherein the charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer,
• and having a clock generator
• having a clock frequency of more than 100 MHz,
• which applies changes in potential at the clock frequency to the gates,
• for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer,
• wherein
• the charge transfer channel
• and one gate or the sequence of two adjoining gates
• has a region of a protuberance
• in which the cross-section in the flow direction first increases by more than 20% and then decreases by more than 20%, and
• which is arranged in a manner extending over the region of one or two mutually adjoining gates, and
• has a region of a constriction
• in which the cross-section in the flow direction decreases continuously in a constant fashion, and
• is arranged at least in the region of the gate upstream of the region of the protuberance or in the regions of the gate upstream of the protuberance and the adjoining gate of the protuberance.