US 12,712,532 B2Granted

Single-to-differential circuit and method for operating the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorChang-Yi Li

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Abstract

The present disclosure provides an integrated circuit, which includes an input stage, a first output stage, and a second output stage. The input stage receives and converts an input clock signal into a first signal and a second signal. The first output stage includes a first inverter and a first buffer circuit. The first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at a first output terminal of the integrated circuit. The second output stage includes a second inverter and a second buffer circuit. The second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at a second output terminal of the integrated circuit. The first output clock signal and the second output clock signal are differential clock signals.

Claims20

Dependent claims

An integrated circuit, comprising:

an input stage, configured to receive an input clock signal, and convert the input clock signal into a first signal and a second signal;
a first output stage, comprising:
a first inverter and a first buffer circuit coupled to a first output terminal of the integrated circuit, wherein the first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at the first output terminal;
and
a second output stage, comprising a second inverter and a second buffer circuit coupled to a second output terminal of the integrated circuit, wherein the second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at the second output terminal,
wherein the first output clock signal and the second output clock signal are differential clock signals,
wherein the input stage comprises:
a third inverter, configured to convert the input clock signal to generate a third signal at a first node;
a fourth inverter, configured to convert the input clock signal to generate the second signal at a second node;
a fifth inverter, configured to convert the third signal to generate the first signal at a third node;
a third buffer circuit, coupled between the input clock signal and the first node;
and
a fourth buffer circuit, coupled between the first node and the second node.

10 more elements

Dependencies are inferred from the claim text.