Constant transconductance-resistance tracking circuit for complementary metal oxide semiconductor amplifiers

An electrical circuit comprising:

• a complementary metal oxide semiconductor (cMOS) analog amplifier comprising:
• an input p-type metal oxide semiconductor (pMOS) transistor;
• and
• an input n-type metal oxide semiconductor (nMOS) transistor;
• and
• a constant transconductance-resistance (gmR) tracking biasing circuit comprising:
• a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror;
• and
• a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, wherein gate electrodes of the first nMOS transistor and the second nMOS transistor are electrically connected together and wherein a drain electrode of the second nMOS transistor is directly connected to the gate electrode of the second nMOS transistor such that the second nMOS transistor is diode-connected,
• the constant gmR tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and
• the bias output signal being configured to control a pMOS transconductance of the input pMOS transistor and an nMOS transconductance of the input nMOS transistor such that a gain of the analog amplifier, having an effective transconductance based on a sum of the pMOS transconductance and the nMOS transconductance, is substantially constant.

A non-transitory computer-readable medium comprising a stored description of a constant transconductance-resistance (gmR) tracking biasing circuit, the constant gmR tracking biasing circuit comprising:

• a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror;
• and
• a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, wherein gate electrodes of the first nMOS transistor and the second nMOS transistor are electrically connected together and wherein a drain electrode of the second nMOS transistor is directly connected to the gate electrode of the second nMOS transistor such that the second nMOS transistor is diode-connected,
• the constant gmR tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and
• the bias output signal being configured to control a pMOS transconductance of an input pMOS transistor and an nMOS transconductance of an input nMOS transistor of an analog circuit, the input pMOS transistor and the input nMOS transistor being connected in series.