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US 12,712,435 B2Granted
Advanced gate driver for improved EMI performance during MOSFET turn-on
AssigneeRenesas Design (UK) Limited
InventorsRakshitha Salian, Vijay Kanagala, Kai-wen Chin
Life of this patent
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Abstract
A gate driver is provided for a switching power converter that charges a gate of the power switch transistor through a gate drive resistance that is varied through four portions of an on-time period for the power switch transistor. In a first portion and a second portion of the on-time period, the gate driver controls the gate drive resistance to be relatively low but then increases the gate driver resistance for a third portion of the on-time period. In a final fourth portion of the on-time period, the gate driver decreases the gate drive resistance. The fourth portion begins during a Miller plateau period for the gate voltage.
Claims18
An adaptive gate driver for a power switch transistor in a switching power converter, comprising:
- a gate drive circuit configured to charge a gate voltage of the power switch transistor through a variable gate drive resistance;
- a first comparator configured to assert a first comparator output signal in response to the gate voltage being greater than a first threshold voltage;
- a second comparator configured to assert a second comparator output signal in response to the gate voltage being greater than a second threshold voltage that is greater than the first threshold voltage;
- and
- an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of an on-time period for the power switch transistor while the first comparator output signal is not asserted and during a second portion of the on-time period for the power switch transistor following the assertion of the first comparator output signal and while the second comparator output signal is not asserted, and to use a second gate drive resistance during a third portion of the on-time period for the power switch transistor after the second comparator output signal is asserted and before a sampling period has expired, and to use a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor after an expiration of the sampling period, wherein the adaptive drive control circuit is further configured to begin a timing of the sampling period in response to the assertion of the second comparator output signal, and wherein the adaptive drive control circuit is further configured to set the second gate drive resistance to be greater than the first gate drive resistance and to be greater than the third gate drive resistance in response to a detection that the switching power converter is in a discontinuous conduction mode of operation.
2 more elements
A method of adapting a gate drive resistance for a power switch transistor in a switching power converter, comprising:
- charging a gate of the power switch transistor through a first gate drive resistance during a first portion of an on-time period for the power switch transistor while a gate voltage of the power switch transistor is less than a first threshold voltage and during a second portion of the on-time period for the power switch transistor while the gate voltage is less than a second threshold voltage that is greater than the first threshold voltage;
- initiating a timing of a sampling period responsive to the gate voltage being greater than the second threshold voltage;
- charging the gate through a second gate drive resistance during a third portion of the on-time period for the power switch transistor while the gate voltage is greater than the second threshold voltage and before an expiration of the sampling period, wherein the second gate drive resistance is greater than the first gate drive resistance;
- sampling the gate voltage at an expiration of the sampling period to provide a sampled gate voltage;
- charging the gate through a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor following the expiration of the sampling period;
- and
- adjusting the second threshold voltage to equal a fraction of the sampled gate voltage.
4 more elements
A switching power converter, comprising:
- an inductor;
- a power switch transistor connected to the inductor;
- and
- a gate drive control circuit configured to:
- charge a gate of the power switch transistor through a first gate drive resistance during a first portion of an on-time period for the power switch transistor and during a second portion of the on-time period for the power switch transistor, wherein the first portion of the on-time period for the power switch transistor is terminated responsive to a gate voltage of the power switch transistor being greater than a first threshold voltage, and wherein the second portion of the on-time period for the power switch transistor is terminated responsive to the gate voltage of the power switch transistor being greater than a second threshold voltage that is greater than the first threshold voltage;
- adapt the first gate drive resistance responsive to a duration of the first portion of the on-time period for the power switch transistor;
- charge the gate through a second gate drive resistance during a third portion of the on-time period for the power switch transistor, wherein the second gate drive resistance is greater than the first gate drive resistance;
- charge the gate through a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor, wherein the second gate drive resistance is greater than the third gate drive resistance;
- begin timing a sampling period in response to a beginning of the third portion of the on-time period for the power switch transistor;
- transition from the third portion of the on-time period for the power switch transistor to the fourth portion of the on-time period for the power switch transistor in response to an expiration of the sampling period;
- sample the gate voltage of the power switch transistor in response to the expiration of the sampling period to provide a sampled gate voltage;
- and
- adapt the second threshold voltage to equal a fraction of the sampled gate voltage.
10 more elements
Dependencies are inferred from the claim text.