Digital electricity controller

A controller for use in a fault managed power (FMP) system, the FMP system including a FMP transmitter connected to a FMP transmission line, the FMP transmitter further connected to a power source and configured to transmit power in pulses, in a low power mode or a high-power mode, over the FMP transmission line during power transfer periods and to isolate the source from the transmission line during power sample periods, the controller comprising:

• a FMP front-end circuit configured to be connected in parallel to the FMP transmission line;
• an output control and conditioning circuit having an input port and including:
• a capacitance connected in parallel across the input port of the output control and conditioning circuit;
• a voltage regulator having an input and an output, the input connected to the capacitance and to the input port of the output control and conditioning circuit;
• an interface device connected to the output of the voltage regulator;
• a processor and memory connected to the output of the voltage regulator, the processor in communication with the interface device and a communication device, the memory storing instructions that when executed by the processor cause one or more of the following:
• the interface device to receive input data from a human operator or a sensor,
• the interface device to present output data for the human operator to observe, or
• the communication device to transmit data to and receive data from the FMP transmitter;
• at least one switch connected between the FMP front-end circuit and the input port of the output control and conditioning circuit;
• wherein the at least one switch is configured to connect the output control and conditioning circuit to the FMP front-end circuit and the FMP transmission line to receive power from the FMP transmission line when the FMP transmitter transmits power, in both the low power mode and the high-power mode, and for electrically isolating the output control and conditioning circuit from the FMP front-end circuit and the FMP transmission line during power sample periods.