Memory devices using defective address information processing circuits, and operating methods, and memory systems thereof

A memory device, comprising:

• a first defective address information memory, wherein the first defective address information memory is configured to store multiple pieces of initial defective address information, and the multiple pieces of initial defective address information comprise initial target defective address information and multiple pieces of initial non-target defective address information, the initial target defective address information being stored in the first defective address information memory after the multiple pieces of initial non-target defective address information;
• a defective address information processing circuit, wherein the defective address information processing circuit is connected to the first defective address information memory, and is configured to:
• compare the initial target defective address information previously stored in the first defective address information memory with each of the multiple pieces of initial non-target defective address information previously stored in the first defective address information memory;
• control whether to process the initial non-target defective address information based on a comparison result, wherein respective comparing sub-circuits of the defective address information processing circuit are configured to operate in parallel to output respective sub-comparison results, and the comparison result is generated based on the respective sub-comparison results;
• in response to one of the sub-comparison results indicating a match between the initial target defective address information and a respective one of the multiple pieces of initial non-target defective address information, generating corresponding defective address information comprising second identification information that comprises a second value, the second value indicating that a corresponding relationship between a defective address and a redundant address in the corresponding defective address information is invalid, and the corresponding defective address information is prohibited to be used;
• and
• output multiple pieces of defective address information corresponding to the multiple pieces of initial defective address information;
• and
• a second defective address information memory, wherein the second defective address information memory is connected to the defective address information processing circuit, and is configured to store the multiple pieces of defective address information.