Voltage scaling based on error rate

A method, comprising:

• receiving, by a physical input/output (PHY I/O) device, memory parity information corresponding to a bit string;
• calculating a parity mismatch value based on a comparison between the received memory parity information and a calculated PHY I/O parity information;
• determining a target parity mismatch value;
• comparing the calculated parity mismatch value and the determined target parity mismatch value;
• and
• regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value.

A system, comprising:

• a memory device comprising a plurality of memory dice, wherein circuitry resident on at least one of the memory dice is configured to:
• write data, received from a physical input/output (PHY I/O) device coupled to the memory device, to the one of the plurality of memory dice;
• read data from the one of the plurality of memory dice;
• append parity information, generated by the circuitry, to the data read from the one of the plurality of memory dice to generate a first bit string comprising the read data and the parity information;
• and
• transmit the first bit string to the PHY I/O device via a channel;
• the PHY I/O device, wherein the PHY I/O device is configured to:
• transmit data to the memory device;
• and
• receive the first bit string comprising the read data and memory parity information transmitted from the memory device via the channel;
• and
• a processing device coupled to the PHY I/O device, wherein the processing device is configured to:
• compare the received memory parity information to PHY I/O parity information calculated by the processing device;
• calculate a parity mismatch value based on the comparison between the received memory parity information and the calculated PHY I/O parity information;
• determine an actual channel error rate based on the calculated parity mismatch value;
• regulate a voltage in response to the calculated parity mismatch value;
• and
• wherein the processing device is further configured to:
• utilize a decoder coupled to the processing device to decode data in a codeword received in the bit string;
• determine an actual total error rate based on the data in the codeword;
• and
• calculate an actual memory device error rate based on a difference between the actual total error rate and the actual channel error rate.

An apparatus, comprising:

• a physical input/output (PHY I/O) device, wherein a processing device is configured to:
• receive a bit string including parity information, provided from a memory device over a channel;
• and
• a processing device coupled to the PHY I/O device, wherein the processing device is configured to:
• calculate a parity mismatch value based on a comparison between memory parity information and calculated PHY I/O parity information determined by the processing device;
• determine an actual channel error rate based on the calculated parity mismatch value;
• and regulate a voltage in response to the determined actual channel error rate;
• and
• wherein the processing device is further configured to:
• compare a target parity mismatch value to the calculated parity mismatch value;
• and
• in response to the calculated parity mismatch value being within a threshold range of the target parity mismatch value, regulate the voltage by maintaining a voltage value.