Memory circuit with multiply-accumulate (MAC) circuit and method of operating the same

A memory circuit, comprising:

• a compute-in-memory (CIM) macro circuit, the CIM macro circuit comprising:
• a memory cell array including rows and columns, and configured to store a set of stored data, the set of stored data being one of a first set of weight signals or a set of inverted weight signals, the set of inverted weight signals being inverted from the first set of weight signals;
• and
• a multiply-accumulate (MAC) circuit coupled to the memory cell array, and configured to generate a first set of data in response to a second set of data and the set of stored data;
• and
• an input output (IO) circuit coupled to the CIM macro circuit, and configured to output a first set of output signals, the IO circuit comprising:
• a write circuit coupled to the memory cell array, and configured to:
• send the first set of weight signals in response to at least a set of enable signals;
• or
• generate the set of inverted weight signals in response to at least a set of inverted enable signals;
• a read circuit coupled to the MAC circuit, and configured to output the first set of output signals in response to at least the first set of data and the set of enable signals;
• a first circuit coupled to the write circuit and the read circuit, and configured to generate the set of enable signals in response to at least the set of stored data in the memory cell array;
• and
• a second circuit coupled to the write circuit and the first circuit, and configured to generate the set of inverted enable signals in response to the set of enable signals;
• a set of word lines coupled to the memory cell array;
• and
• an input driver circuit coupled to the memory cell array by the set of word lines, and being configured to send a set of word line signals on the set of word lines, to generate a count signal, and to send the count signal to the IO circuit.

A method of operating a memory circuit, the method comprising:

• receiving, by a first write circuit, a first set of weight signals;
• generating, by a second write circuit, a set of enable signals in response to at least a count signal, the count signal corresponding to a number of active word lines coupled to a memory cell array;
• generating, by a first circuit, a set of inverted enable signals in response to the set of enable signals, a set of inverted weight signals being inverted from the first set of weight signals;
• performing a write operation of the memory cell array, the performing the write operation of the memory cell array comprising:
• at least one of:
• outputting, by the first write circuit, the first set of weight signals in response to at least the set of enable signals;
• or
• generating, by the first write circuit, the set of inverted weight signals in response to at least the set of inverted enable signals;
• and
• storing a set of stored data in the memory cell array, the set of stored data being one of the first set of weight signals or the set of inverted weight signals;
• performing, by a multiply-accumulate (MAC) circuit, a computing-in memory (CIM) operation between the set of stored data and a first set of input signals thereby generating a first set of data, the MAC circuit being coupled to the memory cell array;
• performing, by a read circuit, a read operation of a column of memory cells in the memory cell array, the performing the read operation of the column of memory cells in the memory cell array comprises:
• generating, by the read circuit coupled to the MAC circuit and the memory cell array, the first set of output signals in response to at least a first set of data, the set of enable signals or the count signal.