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US 12,712,031 B2Granted
Memory system
AssigneeKioxia Corporation
InventorsNaoto Kumano, Kenji Sakurada
Life of this patent
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Abstract
A memory system includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and a controller. The controller is configured to perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on a shift voltage, and to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied.
Claims20
A memory system comprising:
- a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage;
- and
- a controller that stores a first shift voltage, wherein
- the controller is configured to:
- perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on the first shift voltage, and generate a channel matrix that indicates, for each of a plurality of threshold voltage ranges, a number of first memory cells determined to store a first value and a number of first memory cells determined to store a second value,
- determine whether a hard error condition is satisfied based on a number of first memory cells indicated by the generated channel matrix to be in a hard error state, wherein a first memory cell is in the hard error state when a threshold voltage of the first memory cell is lower than a lowest voltage among the plurality of first soft bit voltages or higher than a highest voltage among the plurality of first soft bit voltages, and
- when the hard error condition is satisfied, calculate a second shift voltage based on the channel matrix and update the first shift voltage stored in the controller with the second shift voltage for use in a next execution of the first error correction process.
4 more elements
A memory system comprising:
- a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage;
- and
- a controller that stores a first shift voltage and a second shift voltage, wherein
- the controller is configured to:
- perform a first error correction process for the plurality of first memory cells, based on first hard bit data that is acquired using a first hard bit voltage and first soft bit data acquired using a plurality of first soft bit voltages that are less than the first hard bit voltage, which have been calculated based on the first shift voltage, and a plurality of second soft bit voltages that are greater than the first hard bit voltage, which have been calculated based on the second shift voltage, and generate a channel matrix that indicates, for each of a plurality of threshold voltage ranges, a number of first memory cells determined to store a first value and a number of first memory cells determined to store a second value,
- determine whether each of a first hard error condition and a second hard error condition is satisfied based on a number of first memory cells indicated by the generated channel matrix to be in a hard error state, wherein a first memory cell is in the hard error state when a threshold voltage of the first memory cell is less than a lowest voltage among the plurality of first soft bit voltages or higher than a highest voltage among the plurality of second soft bit voltages, and
- when the first hard error condition is satisfied, correct the first shift voltage, and when the second hard error condition is satisfied, correct the second shift voltage, for use in a next execution of the first error correction process.
4 more elements
Dependencies are inferred from the claim text.