Floating data line circuit and method

A memory circuit comprising:

• first and second write lines coupled to first and second memory segments;
• a power supply node configured to carry a power supply voltage level;
• a reference node configured to carry a reference voltage level;
• a first driving circuit comprising:
• a first PMOS transistor coupled in series with a first inverter between the power supply node and the reference node, wherein the first inverter comprises an input coupled to a first input node of the first driving circuit and an output coupled to the first write line;
• and
• a second inverter coupled between a gate of the first PMOS transistor and a second input node of the first driving circuit;
• a first pre-charge circuit coupled between the power supply node and the output of the first inverter;
• a second driving circuit comprising:
• a second PMOS transistor coupled in series with a third inverter between the power supply node and the reference node, wherein the third inverter comprises an input coupled to a first input node of the second driving circuit and an output coupled to the second write line;
• and
• a fourth inverter coupled between a gate of the second PMOS transistor and a second input node of the second driving circuit;
• and
• a second pre-charge circuit coupled between the power supply node and the output of the third inverter;
• wherein:
• each of the first input node of the first driving circuit and the second input node of the second driving circuit is configured to receive a first data signal, and
• each of the second input node of the first driving circuit and the first input node of the second driving circuit is configured to receive a second data signal.

A method of operating a memory circuit, the method comprising:

• propagating a first data signal to each of a first input node of a first driving circuit of the memory circuit and a second input node of a second driving circuit of the memory circuit;
• and
• propagating a second data signal to each of a second input node of the first driving circuit and a first input node of the second driving circuit, wherein
• the memory circuit comprises:
• first and second write lines coupled to first and second memory segments;
• a power supply node configured to carry a power supply voltage level;
• and
• a reference node configured to carry a reference voltage level, the first driving circuit comprises:
• a first PMOS transistor coupled in series with a first inverter between the power supply node and the reference node, wherein the first inverter comprises an input coupled to the first input node of the first driving circuit and an output coupled to the first write line;
• and
• a second inverter coupled between a gate of the first PMOS transistor and the second input node of the first driving circuit, and the second driving circuit comprises:
• a second PMOS transistor coupled in series with a third inverter between the power supply node and the reference node, wherein the third inverter comprises an input coupled to the first input node of the second driving circuit and an output coupled to the second write line;
• and
• a fourth inverter coupled between a gate of the second PMOS transistor and the second input node of the second driving circuit.