Bit line accumulation readout scheme for an analog in-memory computation processing circuit

A circuit, comprising:

• a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, each column including a bit line connected to the memory cells of the column, and each memory cell storing a bit of weight data for an in-memory computation operation;
• a word line driver circuit for each row having an output connected to drive the word line of the row;
• a row controller circuit coupled to the word line driver circuits and configured to simultaneously actuate a plurality of word lines during said in-memory computation operation;
• and
• a column processing circuit including:
• a discharge time sensing circuit for each column comprising:
• a timing capacitor having a capacitor voltage that is selectively discharged by a discharge current during said in-memory computation operation;
• and
• a comparator circuit configured to control termination of the discharge current in response to a comparison of a bit line voltage to a threshold voltage;
• a bit line clamping circuit configured to clamp the bit line to a clamp voltage following discharge of the bit line to the threshold voltage;
• analog-to-digital conversion circuitry configured to convert the capacitor voltages to digital signals;
• and
• computation circuitry configured to perform digital signal processing calculations on the digital signals and generate a decision output for the in-memory computation operation.

A method, comprising:

• storing bits of weight data for an in-memory computation operation in memory cells of a memory array including plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column;
• simultaneously actuating a plurality of word lines during said in-memory computation operation;
• generating an analog signal indicative of a time taken during said in-memory computation operation to discharge each bit line from a precharge voltage to a threshold voltage;
• converting the analog signals to digital signals;
• and
• performing digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation;
• wherein generating the analog signal comprises:
• charging a timing capacitor to a first voltage level prior to the in-memory computation operation;
• applying a discharge current to the timing capacitor during the in-memory computation operation;
• and
• terminating application of the discharge current when the discharge of the bit line from the precharge voltage reaches the threshold voltage;
• wherein the analog signal is a second voltage level remaining on the timing capacitor after termination of the discharge current application.