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US 12,712,011 B2Granted
Dynamic random access memory system including single-ended sense amplifiers and methods for operating same
AssigneeAtomera Incorporated
InventorRichard S. Roy
Life of this patent
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Abstract
A DRAM system having a first array of DRAM cells, wherein each column of DRAM cells is coupled to a corresponding bit line, and a plurality of single-ended sense amplifiers, each coupled to a corresponding bit line. Each of the single-ended sense amplifiers includes a kick capacitor coupled to the corresponding bit line, a latch circuit having a first internal node for storing a data bit, and an isolation transistor coupling the corresponding bit line to the first internal node of the latch circuit, wherein the corresponding bit line is the only bit line of the first array of DRAM cells coupled to the latch circuit.
Claims48
A dynamic random access memory (DRAM) system comprising:
- a first array of DRAM cells arranged in a plurality of rows and columns, wherein each of the columns of DRAM cells is coupled to a corresponding bit line;
- and
- a plurality of single-ended sense amplifiers, each coupled to a corresponding bit line of the first array of DRAM cells, wherein each of the single-ended sense amplifiers comprises:
- a kick capacitor coupled to the corresponding bit line;
- a latch circuit having a first internal node for storing a data value;
- and
- an isolation transistor coupling the corresponding bit line to the first internal node of the latch circuit, wherein the corresponding bit line is the only bit line of the first array of DRAM cells coupled to the latch circuit.
4 more elements
A method of operating a dynamic random access memory (DRAM) system comprising:
- pre-charging a bit line coupled to a DRAM cell to ground;
- pre-charging first and second internal nodes of a sense amplifier latch to ground;
- driving first and second supply voltage terminals of the sense amplifier latch to ground;
- activating a word line coupled to the DRAM cell, thereby causing the DRAM cell to develop a read voltage on the bit line;
- activating a kick capacitor to drive down the read voltage developed on the bit line;
- then
- coupling the bit line to the first internal node of the sense amplifier latch, thereby applying the read voltage developed on the bit line to the first internal node of the sense amplifier latch;
- then
- isolating the bit line from the first internal node of the sense amplifier latch;
- driving the first supply voltage terminal of the sense amplifier latch to a first supply voltage above ground, and driving the second supply voltage terminal of the sense amplifier latch to a second supply voltage;
- and then
- coupling the bit line to the first internal node of the sense amplifier latch.
9 more elements
A dynamic random access memory (DRAM) system comprising:
- a first integrated circuit chip including a plurality of processors;
- a second integrated circuit chip including a first plurality of independent DRAM arrays, wherein each of the first plurality of independent DRAM arrays is connected to a corresponding one of the plurality of processors on the first integrated circuit chip;
- and
- refresh control circuitry located on the first integrated circuit chip, wherein the refresh control circuitry initiates refresh operations to the first plurality of DRAM arrays on the second integrated circuit chip.
1 more element
A dynamic random access memory (DRAM) system comprising:
- a first integrated circuit chip including a plurality of processors;
- a second integrated circuit chip including a first plurality of independent DRAM sectors, wherein each of the first plurality of independent DRAM sectors is connected to a corresponding one of the plurality of processors on the first integrated circuit chip via a first plurality of through silicon via (TSV) interconnect structures;
- and
- a third integrated circuit chip including a second plurality of independent DRAM sectors, wherein each of the second plurality of independent DRAM sectors is connected to a corresponding one of the plurality of processors on the first integrated circuit chip via a second plurality of TSV interconnect structures, wherein the second plurality of TSV interconnect structures extend through the first integrated circuit chip.
1 more element
A dynamic random access memory (DRAM) unit cell located on an integrated circuit chip, wherein the DRAM unit cell comprises:
- a plurality of through silicon vias (TSVs) that extend through the integrated circuit chip;
- a first plurality of DRAM banks that are aligned along a first axis;
- and
- a second plurality of DRAM banks that are aligned along the first axis, wherein the plurality of TSVs are located between the first and second plurality of DRAM banks along the first axis, wherein the plurality of TSVs transmit address and control signals for accessing the first and second plurality of DRAM banks, and wherein the plurality of TSVs transmit read and write data for the first and second plurality of DRAM banks, wherein each of the first and second plurality of DRAM banks includes:
- a plurality of strips, wherein each strip includes:
- a plurality of corresponding rows of DRAM bit cells of the DRAM bank;
- a first primary sense amplifier circuit located adjacent to a first one of the plurality of corresponding rows of DRAM bit cells, wherein a first subset of the DRAM bit cells is coupled to the first primary sense amplifier circuit;
- and
- a second primary sense amplifier circuit located adjacent to a last one of the plurality of corresponding rows of DRAM bit cells, wherein a second subset of the DRAM bit cells are coupled to the second primary sense amplifier circuit.
6 more elements
A dynamic random access memory (DRAM) unit cell comprising:
- a first memory bank having:
- a plurality of rows and columns of DRAM cells, wherein the plurality of rows of the first memory bank are divided into N DRAM strips, wherein N is an integer greater than one, and wherein each of the N DRAM strips of the first memory bank includes a plurality of consecutive rows of the DRAM cells of the first memory bank;
- a plurality of N+1 primary sense amplifier circuits, wherein each of the N DRAM strips of the first memory bank is coupled to a corresponding pair of the primary sense amplifier circuits of the first memory bank;
- a second memory bank having:
- a plurality of rows and columns of DRAM cells, wherein the plurality of rows of the second memory bank are divided into N DRAM strips, and wherein each of the N DRAM strips of the second memory bank includes a plurality of consecutive rows of the DRAM cells of the second memory bank;
- a plurality of N+1 primary sense amplifier circuits, wherein each of the N DRAM strips of the second memory bank is coupled to a corresponding pair of the primary sense amplifier circuits of the second memory bank;
- and
- a secondary sense amplifier circuit located between the first and second memory banks, wherein the secondary sense amplifier circuit is coupled to each of the primary sense amplifier circuits of the first and second memory banks.
5 more elements
A dynamic random access memory (DRAM) system comprising:
- a first set of DRAM cells arranged in a plurality of rows and four columns, wherein each of the four columns of DRAM cells in the first set of DRAM cells is coupled to a corresponding bit line of a first group of four bit lines;
- a second set of DRAM cells arranged in a plurality of rows and four columns, wherein each of the four columns of DRAM cells in the second set of DRAM cells is coupled to a corresponding bit line of a second group of four bit lines;
- and
- a first single-ended sense amplifier pair located between the first and second sets of DRAM cells, wherein the first single-ended sense amplifier pair comprises:
- a first single-ended sense amplifier;
- a second single-ended sense amplifier;
- a first transistor for selectively coupling and decoupling the first single-ended sense amplifier to a first bit line of the first group of bit lines;
- a second transistor for selectively coupling and decoupling the first single-ended sense amplifier to a first bit line of the second group of bit lines, wherein the first and second transistors are controlled such that the first single-ended sense amplifier is coupled to, at most, one bit line at a time;
- a third transistor for selectively coupling and decoupling the second single-ended sense amplifier to a second bit line of the first group of bit lines;
- a fourth transistor for selectively coupling and decoupling the second single-ended sense amplifier to a second bit line of the second group of bit lines, wherein the third and fourth transistors are controlled such that the second single-ended sense amplifier is coupled to, at most, one bit line at a time.
7 more elements
Dependencies are inferred from the claim text.