Sequenced activation of memory components
AssigneeMicron Technology, Inc.
InventorsShawn Storm, Brittany A. Boyd, Christopher Kuhn, Eric S. Nelson, Craig A. Farrer, Kazuo Shibata
Life of this patent
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Abstract
A method includes providing, in accordance with a memory component activation sequence, a first activation power to a first memory component of a plurality of memory components for a first time period, where the first activation power is provided in the absence of providing an activation power to at least one other memory component of the plurality of memory components during the first time period. The method includes providing, in accordance with the memory component activation sequence, a second activation power to a second memory component for a second time period.
Claims20
A method comprising:
- providing, in accordance with a memory component activation sequence, a first activation power to a first memory component of a plurality of memory components within a memory device for a first time period, wherein the first activation power is provided in the absence of providing an activation power to at least one other memory component of the plurality of memory components within the memory device during the first time period;
- and
- providing, in accordance with the memory component activation sequence, a second activation power to a second memory component for a second time period.
An apparatus comprising:
- a first memory component of a plurality of memory components within a memory device;
- a second memory component of the plurality of memory components within the memory device;
- a voltage regulator coupled to the first memory component and the second memory component;
- and
- activation sequence circuitry configured to activate the first memory component and the second memory component in accordance with a memory component activation sequence by:
- providing, via the voltage regulator, a first activation power to the first memory component for a first time period to activate the first memory component in the absence of providing an activation power to at least one other memory component of the plurality of memory components during the first time period;
- and
- providing, via the voltage regulator, a second activation power to the second memory component for a second time period to activate the second memory component.
A system comprising:
- a plurality of packages within a memory device including a plurality of stacked memory components, the plurality of stacked memory components including a first memory component, a second memory component, and a third memory component;
- a voltage regulator coupled to at least one memory component of the plurality of stacked memory components;
- and
- activation sequence circuitry configured to:
- provide, in accordance with a memory component activation sequence, a respective activation power to each package of the plurality of packages in the absence of providing an activation power to at least one other package of the plurality of packages;
- and
- provide, in accordance with the memory component activation sequence, a respective activation power to each memory component of the plurality of stacked memory components in a respective package in the absence of providing an activation power to at least one other memory component of the respective package.
Dependencies are inferred from the claim text.