Multi-level bit-cell with non-linear polar material

A system comprising:

• a processor;
• a memory coupled to the processor;
• and
• a communication circuitry coupled to the processor, wherein the memory includes a bit-cell that includes:
• a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line;
• and
• a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, wherein the capacitor includes at least four stable states,
• and wherein the capacitor includes:
• a first capacitor with a first non-linear polar material;
• and
• a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.

A method comprising:

• forming a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line;
• and
• forming a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states, and wherein the capacitor includes:
• a first capacitor with a first non-linear polar material;
• and
• a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.