Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
AssigneeRambus Inc.
InventorYohan Frans
Life of this patent
Estimating the term…
Abstract
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
Claims20
A memory device, comprising:
- a first memory die coupled to a data pin and including a first storage array;
- a second memory die stacked with the first memory die and including a second storage array;
- in response to a read command, the first storage array and the second storage array to perform parallel read access operations to access disaggregated read data;
- serialization circuitry to serialize the disaggregated read data into aggregated read data;
- and
- wherein the data pin is to transmit the aggregated read data in the form of serialized read data to a memory controller.
A method of operation in a memory device, the memory device having a data pin, a first memory die coupled to the data pin, and a second memory die stacked with the first memory die, the method comprising:
- performing parallel read access operations to the first memory die and the second memory die to access disaggregated read data in response to receiving a read command;
- serializing the disaggregated read data into serialized aggregated read data;
- and
- transmitting, with the data pin, the serialized aggregated read data to a memory controller.
A dynamic random access memory (DRAM) device, comprising:
- multiple DRAM memory die stacked in a vertical relationship, the multiple DRAM memory die having multiple storage arrays;
- in response to receiving a read command, the multiple storage arrays to perform parallel read access operations to access disaggregated read data;
- serialization circuitry to serialize the disaggregated read data into serialized read data;
- and
- a data pin to transmit the serialized read data to a memory controller.
Dependencies are inferred from the claim text.