Driving circuit and electronic device

A driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises:

• a first transistor connected to a first terminal receiving a start signal, and to a first node, the first transistor comprising a gate connected to a clock terminal receiving a clock signal;
• a second transistor connected between the first node and a second node, and comprising a gate connected to a second terminal receiving a first voltage;
• a third transistor connected between a third terminal receiving a second voltage higher than the first voltage, and a third node, the third transistor comprising a gate connected to the first node;
• a fourth transistor connected between the third node and the second terminal, and comprising a gate connected to the second node;
• a fifth transistor connected between an output terminal and the second terminal, and comprising a gate connected to the second node;
• a sixth transistor connected between the third terminal and the output terminal, and comprising a gate connected to the third node;
• a seventh transistor connected between the third node and a fourth terminal receiving a third voltage lower than the first voltage, the seventh transistor comprising a gate connected to a reset terminal;
• and
• an eighth transistor connected between the third terminal and the first node, and comprising a gate connected to the reset terminal.

An electronic device comprising:

• a controller configured to output a plurality of clock signals;
• a power supply circuit configured to output a plurality of voltages;
• and
• a driving circuit configured to output a gate signal based on the plurality of clock signals and the plurality of voltages,
• wherein the driving circuit comprises a plurality of stages, wherein each of the plurality of stages comprises:
• a first transistor connected to a first terminal receiving a start signal, and to a first node, the first transistor comprising a gate connected to a clock terminal receiving one of the clock signals;
• a second transistor connected between the first node and a second node, and comprising a gate connected to a second terminal receiving a first voltage among the plurality of voltages;
• an inverter connected between a third terminal receiving a second voltage among the plurality of voltages, and the second terminal, the inverter being configured to control a voltage of a third node to be a voltage obtained by inverting a voltage level of the first node or the second node;
• a pull-down transistor connected between an output terminal and the second terminal, and comprising a gate connected to the second node;
• a pull-up transistor connected between the third terminal and the output terminal, and comprising a gate connected to the third node;
• and
• a reset circuit configured to reset the second node or the third node,
• wherein the reset circuit comprises:
• a third transistor connected between the third node and the second terminal, and comprising a gate connected to a first reset terminal;
• and
• a fourth transistor connected between the third terminal and the first node, and comprising a gate connected to a second reset terminal,
• wherein the third transistor is a P-channel transistor, and the fourth transistor is an N-channel transistor,
• wherein a timing at which a first reset signal input to the first reset terminal of the third transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal of the fourth transistor is a gate-on voltage are the same.

An electronic device comprising:

• a controller configured to receive an on-operation signal from a processor and output a reset signal based on the on-operation signal;
• and
• a driving circuit comprising a stage configured to receive the reset signal and reset a control node,
• wherein the stage comprises:
• a first transistor connected to a first terminal receiving a start signal, and to a first node, the first transistor comprising a gate connected to a clock terminal receiving a clock signal;
• a second transistor connected between the first node and a second node, and comprising a gate connected to a second terminal receiving a first voltage;
• an inverter connected between a third terminal receiving a second voltage, and the second terminal, the inverter being configured to control a voltage of the control node to be a voltage obtained by inverting a voltage level of the first node or the second node;
• a pull-down transistor connected between an output terminal and the second terminal, and comprising a gate connected to the second node;
• a pull-up transistor connected between the third terminal and the output terminal, and comprising a gate connected to the control node;
• and
• a reset transistor connected between the control node and the second terminal, and comprising a gate connected to a reset terminal receiving the reset signal,
• wherein the stage further comprises a second reset transistor connected between the third terminal and the first node, and comprising a gate connected to a second reset terminal,
• wherein the reset transistor is a P-channel transistor, and the second reset transistor is an N-channel transistor,
• wherein the controller is further configured to control a timing at which a reset signal input to the reset terminal of the reset transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal of the second reset transistor is a gate-on voltage to be the same.