System, method, device, processor, and storage medium thereof for implementing large-scale FIFO data processing based on DDR

A system for implementing large-scale FIFO data processing based on DDR, the system comprising:

• an ingress asynchronous clock domain FIFO, with independent write clocks and read clocks, independently setting a write data bit width and a read data bit width for data writing operations;
• a burst read and write data block chain table, connected with the ingress asynchronous clock domain FIFO, for writing a data block chaining table and reading the data block chaining table by setting of the data bit width and the data block length;
• a DDR4 AXI interface, connected with the burst read and write data block chain table, for interacting with a flow control state machine and the burst read and write data block chain table;
• an egress asynchronous clock domain FIFO, connected with the burst read and write data block chain table, with independent write clocks and read clocks, setting the write data bit width and read data bit width settings independently for data output operations;
• and
• the flow control state machine, connected with the ingress asynchronous clock domain FIFO, the DDR4 AXI interface, and the egress asynchronous clock domain FIFO, used for data flow control to monitor writes and reads of data streams to the ingress asynchronous clock domain FIFO, the DDR4 AXI interface and the egress asynchronous clock domain FIFO,
• wherein the burst read and write data block chain table includes a counting monitoring variable to detect the number of operations of the ingress asynchronous clock domain FIFO and the egress asynchronous clock domain FIFO, and counts and monitors data writing and reading out of the DDR4 AXI interface.