Reducing latency for memory operations in a memory controller
AssigneeMicron Technology, Inc.
InventorTony Brewer
Life of this patent
Estimating the term…
Abstract
Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.
Claims20
An apparatus comprising:
- a memory controller configured to perform operations comprising:
- selecting a memory request from a first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the first input queue storing memory requests from a requesting processor that are received over a network-on-chip interface and the second input queue storing memory requests from an atomic unit of the memory controller;
- determining that the memory request is a write request to write a requested value to a requested location in a memory of a memory array;
- responsive to determining that the memory request is a write request:
- sending a response to the requesting processor over the network-on-chip interface, the response sent prior to performing the write request;
- and
- performing the write request to write the request value to the requested location in memory after sending the response to the requesting processor and after all other memory requests that were responded to prior to the memory request have been serviced, but prior to servicing any memory requests responded to after the response has been sent.
A method comprising:
- at a memory controller:
- selecting a memory request from a first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the first input queue storing memory requests from a requesting processor that are received over a network-on-chip interface and the second input queue storing memory requests from an atomic unit of the memory controller;
- determining that the memory request is a write request to write a requested value to a requested location in a memory of a memory array;
- responsive to determining that the memory request is a write request:
- sending a response to the requesting processor over the network-on-chip interface, the response sent prior to performing the write request;
- and
- performing the write request to write the request value to the requested location in memory after sending the response to the requesting processor and after all other memory requests that were responded to prior to the memory request have been serviced, but prior to servicing any memory requests responded to after the response has been sent.
A non-transitory machine-readable medium, storing instructions, which when executed by a machine, causes the machine to perform operations comprising:
- selecting a memory request from a first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the first input queue storing memory requests from a requesting processor that are received over a network-on-chip interface and the second input queue storing memory requests from an atomic unit of the memory controller;
- determining that the memory request is a write request to write a requested value to a requested location in a memory of a memory array;
- responsive to determining that the memory request is a write request:
- sending a response to the requesting processor over the network-on-chip interface, the response sent prior to performing the write request;
- and
- performing the write request to write the request value to the requested location in memory after sending the response to the requesting processor and after all other memory requests that were responded to prior to the memory request have been serviced, but prior to servicing any memory requests responded to after the response has been sent.
Dependencies are inferred from the claim text.