Power loss protection in memory sub-systems
AssigneeMicron Technology, Inc.
InventorAndrew M. Kowles
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
Claims20
A system comprising:
- a plurality of memory components comprising non-volatile memory components and a volatile cache;
- and
- a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
- detecting data written to the volatile cache;
- identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
- accessing the data written to the volatile cache;
- and
- moving the data to the portion of the non-volatile memory components.
A method comprising:
- a plurality of memory components comprising non-volatile memory components and a volatile cache;
- and
- a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
- detecting data written to the volatile cache;
- identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
- accessing the data written to the volatile cache;
- and
- moving the data to the portion of the non-volatile memory components.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
- a plurality of memory components comprising non-volatile memory components and a volatile cache;
- and
- a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
- detecting data written to the volatile cache;
- identifying, from among multiple portions of the non-volatile memory components, a portion having a lower program latency relative to other portions of the non-volatile memory components based on a ranking of program latency of the multiple portions;
- accessing the data written to the volatile cache;
- and
- moving the data to the portion of the non-volatile memory components.
Dependencies are inferred from the claim text.