Cache memory controller for system including plurality of memory devices and operating method of cache memory controller

A cache memory controller comprising:

• an internal memory configured to store a plurality of cost data sets and pieces of weight data on a plurality of internal elements included in the plurality of cost data sets, the plurality of cost data sets being related to data access;
• and
• a logic circuit configured to
• generate a first cost data set corresponding to data access to a first memory and a second cost data set corresponding to data access to a second memory,
• determine a target memory out of the first memory and the second memory, based on a weighted sum of the first cost data set and a weighted sum of the second cost data set that are calculated based on the pieces of the weight data, and
• select a cache line to be replaced, out of cache lines in which data read from the target memory is stored, from among a plurality of cache lines included in a cache memory, when a cache miss occurs after the cache memory is full of data,
• wherein the cache memory controller is configured to control the cache memory including the plurality of cache lines configured to temporarily store data from the first memory or the second memory.