DDR buffer device equalization for self-training mode
AssigneeAdvanced Micro Devices, Inc.
InventorsTsun-Ho Liu, David Da-Wei Lin, Aaron John Nygren
Life of this patent
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Abstract
Embodiments herein describe a method and system for configuring device equalization self-training mode (DESTM) controls using in-band signaling, the DESTM controls including at least setting a minimum duration time, using a host to enable the DESTM controls, triggering a buffer to perform a self-training mode, sending linear-feedback shift register (LFSR) patterns to the buffer for the minimum duration time, and waiting for the minimum completion time to end before disabling the DESTM. The minimum duration time indicates a time that the self-training mode is active and is predefined. The buffer executes the self-training mode within the predefined minimum duration time.
Claims20
An apparatus comprising:
- a host processor configured to:
- configure device equalization self-training mode (DESTM) controls using in-band signaling over a double data rate (DDR) interface, the DESTM controls including at least setting a minimum duration time;
- enable the DESTM controls;
- trigger a data buffer to perform a self-training mode;
- send linear-feedback shift register (LFSR) patterns to the data buffer for the minimum duration time via the DDR interface;
- and
- wait for a minimum completion time to end before disabling the DESTM, wherein the DESTM controls are configured without using sideband signals.
A memory comprising:
- a data buffer including interface logic and data path logic configured to:
- configure device equalization self-training mode (DESTM) controls using in-band signaling over a double data rate (DDR) interface, the DESTM controls including at least setting a minimum duration time;
- enable the DESTM controls;
- trigger the data buffer to perform a self-training mode;
- send linear-feedback shift register (LFSR) patterns to the data buffer for the minimum duration time via the DDR interface;
- and
- wait for a minimum completion time to end before disabling the DESTM, wherein the DESTM controls are configured without using sideband signals.
A system comprising:
- a memory;
- and
- a host processor in communication with the memory, the host processor configured to:
- configure device equalization self-training mode (DESTM) controls using in-band signaling over a double data rate (DDR) interface, the DESTM controls including at least setting a minimum duration time;
- enable the DESTM controls;
- trigger a data buffer in the memory to perform a self-training mode;
- send linear-feedback shift register (LFSR) patterns to the data buffer for the minimum duration time;
- and
- wait for a minimum completion time to end before disabling the DESTM, wherein the DESTM controls are configured without using sideband signals.
Dependencies are inferred from the claim text.