Processor power management using instruction throttling

A method comprising:

• determining, by a throttling control circuit, a power dial value based on a cache miss and a level of a cache in which the cache miss occurred;
• writing, by the throttling control circuit, the power dial value to a register of a processor core including a processor pipeline configured to execute instructions, wherein the power dial value indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline;
• and
• responsive to an active cache miss, stalling removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

An integrated circuit for executing instructions comprising:

• a processor core including a processor pipeline configured to execute instructions;
• a level-one cache configured to store data passing between the processor pipeline and an outer memory system;
• a set of miss status holding registers that are each configured to store data describing a pending miss in the level-one cache;
• a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline;
• a throttling control circuit configured to determine the power dial value based on a cache miss and store the power dial value in the register;
• and
• an instruction throttling circuit configured to periodically stall update of miss status holding registers in the set of miss status holding registers for a number of clock cycles that is determined based on the power dial value.