Chip set central processing unit cross reference code aligned basic input/output system for seamless boot

A system comprising:

• a processor;
• a data bus coupled to the processor;
• and
• a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for:
• identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture, the processor architecture comprising at least one of a baseline processor architecture and a derived processor architecture;
• performing a firmware compatibility management operation, the firmware compatibility management operation managing compatibility of a distributed BIOS to support a baseline processor architecture version of the distributed BIOS and a derived processor architecture version of the distributed BIOS, the baseline processor architecture version of the distributed BIOS including a baseline processor architecture firmware component, the derived processor architecture version including an associated best known configuration of a derived firmware component;
• providing the information handling system with the distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the particular firmware configuration comprising a particular set of firmware components, the particular set of firmware components being based upon at least one of the processor architecture version and the derived processor architecture version;
• and,
• booting the information handling system using the particular firmware configuration based upon at least one of the baseline processor architecture and the derived processor architecture version.

A non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for:

• identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture, the processor architecture comprising at least one of a baseline processor architecture and a derived processor architecture;
• performing a firmware compatibility management operation, the firmware compatibility management operation managing compatibility of a distributed BIOS to support a baseline processor architecture version of the distributed BIOS and a derived processor architecture version of the distributed BIOS, the baseline processor architecture version of the distributed BIOS including a baseline processor architecture firmware component, the derived processor architecture version including an associated best known configuration of a derived firmware component;
• providing the information handling system with the distributed BIOS, the distributed BIOS comprising a particular firmware configuration, the particular firmware configuration comprising a particular set of firmware components, the particular set of firmware components being based upon at least one of the processor architecture version and the derived processor architecture version;
• and,
• booting the information handling system using the particular firmware configuration based upon at least one of the baseline processor architecture and the derived processor architecture version.