US 12,710,926 B1Granted

Integrated circuit for vector compute engine

AssigneeAmazon Technologies, Inc.

InventorsPaul Gilbert Meyer, Sundeep Amirineni, Ron Diamant

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Abstract

An integrated circuit device for vector computations can include multiple computational circuit blocks coupled in series in a pipeline. Each computational circuit block can include an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, and a primary result output. The ALU circuit is programmable to perform a computational operation on the first numeric input and the second numeric input to generate the primary result output. Each computational circuit block can also include an output register to receive the primary result output of the ALU and provide the primary result output of the ALU circuit as a primary output of the computational circuit block, and one or more feedback registers to receive the primary result output of the ALU and provide the primary result output of the ALU circuit to a previous computational circuit block of the pipeline.

Claims21

Dependent claims

An integrated circuit device comprising:

a plurality of computational circuit blocks coupled in series in a pipeline, wherein each computational circuit block includes:
an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, and a primary result output, wherein the ALU circuit is programmable to perform a computational operation on the first numeric input and the second numeric input to generate the primary result output;
a first input multiplexor operable to select one of a plurality of inputs of the computational circuit block as the first numeric input to the ALU circuit;
a second input multiplexor operable to select one of the plurality of inputs of the computational circuit block as the second numeric input to the ALU circuit;
an output register configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit as a primary output of the computational circuit block;
feedback circuitry including one or more feedback registers each configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit to a previous computational circuit block of the pipeline;
and
bypass circuitry including one or more bypass circuits each including a bypass multiplexor coupled to a bypass delay register, and operable to independently select one of the plurality of inputs of the computational circuit block to output to a next computational circuit block of the pipeline.

5 more elements

An integrated circuit device comprising:

a plurality of computational circuit blocks coupled in series in a pipeline, wherein each computational circuit block includes:
an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, and a primary result output, wherein the ALU circuit is programmable to perform a computational operation on the first numeric input and the second numeric input to generate the primary result output;
an output register configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit as a primary output of the computational circuit block;
a first feedback register configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit to a previous computational circuit block of the pipeline;
and
a second feedback register configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit to the previous computational circuit block of the pipeline.

3 more elements

An integrated circuit device comprising:

a plurality of computational circuit blocks coupled in series in a pipeline, wherein each computational circuit block includes:
an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, and a primary result output, wherein the ALU circuit is programmable to perform a computational operation on the first numeric input and the second numeric input to generate the primary result output;
an output register configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit as a primary output of the computational circuit block;
feedback circuitry including one or more feedback registers each configured to receive the primary result output of the ALU circuit and provide the primary result output of the ALU circuit to a previous computational circuit block of the pipeline;
and
a plurality of bypass circuits arranged in parallel, wherein each bypass circuit includes a bypass multiplexor coupled to a bypass delay register, and each bypass circuit is operable to independently select one of a plurality of inputs of the computational circuit block to output to a next computational circuit block of the pipeline.

3 more elements

Dependencies are inferred from the claim text.