Floating-point adder with in-path subnormal handling

An adder circuitry for adding a first operand and a second operand, wherein the first operand comprises a first exponent and a first mantissa, the second operand comprises a second exponent and a second mantissa, and the adder circuitry comprises:

• an exponent subtractor, configured to receive the first exponent and the second exponent for computing an exponent difference between the first exponent and the second exponent;
• a near-path logic circuit, coupled to the exponent subtractor for receiving the exponent difference, and configured to receive the first mantissa and the second mantissa for computing a near-path result according to the exponent difference, the first mantissa and the second mantissa;
• a far-path logic circuit, coupled to the exponent subtractor for receiving the exponent difference, and configured to receive the first mantissa and the second mantissa for computing a far-path result according to the exponent difference, the first mantissa and the second mantissa;
• and
• a selection logic, coupled to the exponent subtractor, the near-path logic circuit and the far-path logic circuit for receiving the exponent difference, the near-path result and the far-path result, and configured to select one of the near-path result and the far-path result as an adder output according to the exponent difference;
• wherein the near-path logic circuit comprises:
• a first shifter, configured to receive the first mantissa and perform a shifting operation upon the first mantissa to generate a first shifted result;
• a second shifter, configured to receive the second mantissa and perform the shifting operation upon the second mantissa to generate a second shifted result;
• a first mantissa subtractor, configured to receive the first mantissa and the second mantissa, and compute a first subtraction result by subtracting the second mantissa from the first mantissa;
• a second mantissa subtractor, configured to receive the second mantissa and the first mantissa, and compute a second subtraction result by subtracting the first mantissa from the second mantissa;
• a third mantissa subtractor, configured to receive the second mantissa and the first shifted result, and compute a third subtraction result by subtracting the first shifted result from the second mantissa;
• a fourth mantissa subtractor, configured to receive the first mantissa and the second shifted result, and compute a fourth subtraction result by subtracting the second shifted result from the first mantissa;
• and
• a mid-selection logic coupled to the first mantissa subtractor, the second mantissa subtractor, the third mantissa subtractor, and the fourth mantissa subtractor for receiving the first subtraction result, the second subtraction result, the third subtraction result, and the fourth subtraction result, wherein the mid-selection logic selects one of the first subtraction result, the second subtraction result, the third subtraction result, and the fourth subtraction result.