Overlay mark, overlay error measurement method for wafer, and wafer stacking method
AssigneeWuhan Xinxin Semiconductor Manufacturing Co., Ltd.
InventorsYicheng Feng, Yuheng Huang, Bang Chen
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Abstract
The present disclosure provides an overlay mark, an overlay error measurement method for a wafer, and a wafer stacking method. The overlay mark includes a first overlay mark disposed on a first layer, and a second overlay mark disposed on a second layer. The first layer and the second layer are stacked. The first overlay mark includes at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape. The second overlay mark includes a second overlay sub-mark, and the second overlay sub-mark is in a center-symmetrical shape including a plurality of linear graphics.
Claims19
An overlay mark, comprising:
- a first overlay mark disposed on a first layer, and a second overlay mark disposed on a second layer;
- wherein the first layer and the second layer are stacked;
- the first overlay mark comprises at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape;
- wherein the first overlay mark is configured to measure an overlay error of a wafer required to be subjected to a circular hole-opening process, and the first overlay mark is formed at the same time as a circular hole is formed by filling conductive material in the circular hole during the circular hole-opening process;
- the first overlay mark is at least one conductive hole defined on the first layer for electrically connecting the first layer and the second layer;
- the second overlay mark comprises a second overlay sub-mark, and the second overlay sub-mark is in a center-symmetrical shape comprising a plurality of linear graphics.
An overlay error measurement method for a wafer, comprising:
- determining a first overlay mark on a first layer and a second overlay mark on a second layer;
- wherein the first layer and the second layer are stacked;
- the first overlay mark comprises at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape;
- the second overlay mark comprises a second overlay sub-mark, and the second overlay sub-mark is in a center-symmetrical shape comprising a plurality of linear graphics;
- and
- measuring and obtaining an overlay error of the first layer based on the first overlay mark and the second overlay mark;
- wherein the first overlay mark is configured to measure the overlay error of a wafer required to be subjected to a circular hole-opening process, and the first overlay mark is formed at the same time as a circular hole is formed by filling conductive material in the circular hole during the circular hole-opening process;
- the first overlay mark is at least one conductive hole defined on the first layer for electrically connecting the first layer and the second layer.
A wafer stacking method, comprising:
- bonding a first wafer to a second wafer;
- wherein a first overlay mark is formed on the first wafer;
- the first overlay mark comprises at least one first overlay sub-mark, and each of the at least one first overlay sub-mark is circular in shape;
- a second overlay mark is formed on the second wafer;
- determining the first overlay mark on the first wafer and the second overlay mark on the second wafer;
- measuring and obtaining an overlay error of the first wafer based on the first overlay mark and the second overlay mark;
- and
- feedbacking the overlay error to an exposure system to compensate for a preparation process of a next batch of wafers;
- wherein the first overlay mark is configured to measure the overlay error of a wafer required to be subjected to a circular hole-opening process, and the first overlay mark is formed at the same time as a circular hole is formed by filling conductive material in the circular hole during the circular hole-opening process;
- the first overlay mark is at least one conductive hole defined on the first wafer for electrically connecting the first wafer and the second wafer.
Dependencies are inferred from the claim text.