Package comprising sidewall interconnects configured for power routing
AssigneeQUALCOMM Incorporated
InventorsXia Li, Xuefeng Zhang, Aniket Patil
Life of this patent
Estimating the term…
Abstract
A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.
Claims20
A device comprising:
- a package comprising:
- a package substrate;
- a first integrated device coupled to the package substrate through a first plurality of bump interconnects, wherein the first plurality of bump interconnects are coupled to and touch the first integrated device and the package substrate;
- a plurality of post interconnects located at least partially in an encapsulation layer;
- a metallization portion coupled to the plurality of post interconnects;
- an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer is coupled to and touches the package substrate and the metallization portion;
- a second integrated device coupled to the metallization portion through a second plurality of bump interconnects, wherein the second plurality of bump interconnects are coupled to and touch the second integrated device and the metallization portion;
- and
- a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.
A device comprising:
- a package comprising:
- a package substrate;
- a first integrated device coupled to the package substrate through a first plurality of bump interconnects, wherein the first plurality of bump interconnects are coupled to and touches the first integrated device and the package substrate;
- a plurality of post interconnects located at least partially in an encapsulation layer;
- a metallization portion coupled to the plurality of post interconnects;
- an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer is coupled to and touches the package substrate and the metallization portion,
- a second integrated device coupled to the metallization portion through a second plurality of bump interconnects, wherein the second plurality of bump interconnects are coupled to and touches the second integrated device and the metallization portion;
- and
- a plurality of package interconnects coupled to the encapsulation layer and the metallization portion, wherein the plurality of package interconnects are embedded in the encapsulation layer.
Dependencies are inferred from the claim text.