Fabricating method of semiconductor die with tapered sidewall in package

A method for forming a chip package structure, comprising:

• dicing a semiconductor wafer to form a first semiconductor die and a second semiconductor die, wherein the first semiconductor die has a first tapered sidewall and a first vertical sidewall opposite to the first tapered sidewall, and the second semiconductor die has a second tapered sidewall and a second vertical sidewall opposite to the second tapered sidewall;
• mounting the first and second semiconductor dies over an interposer substrate, wherein the first tapered sidewall faces the second tapered sidewall;
• forming a first encapsulating layer over the interposer substrate between the first tapered sidewall and second tapered sidewall;
• and
• forming a second encapsulating layer over the interposer substrate and extending along edges of the interposer substrate, to surround the first and the second semiconductor dies and the first encapsulating layer,
• wherein top surfaces of the first and the second semiconductor dies are exposed from the first encapsulating layer and the second encapsulating layer, and
• wherein the first encapsulating layer between the first tapered sidewall and second tapered sidewall has a top width and a bottom width less than the top width.

A method for forming a chip package structure, comprising:

• dicing a semiconductor wafer to form a first semiconductor die and a second semiconductor die, wherein the first semiconductor die has a first sidewall with a vertical contour and a second sidewall with a contour different than the vertical contour and opposite to the first sidewall, and the second semiconductor die has a third sidewall with a vertical contour and a fourth sidewall with a contour different than the vertical contour of the third sidewall and opposite to the third sidewall;
• mounting the first semiconductor die and the second semiconductor die over an organic interposer substrate, wherein the second sidewall adjacent to and fourth sidewall;
• forming a first encapsulating layer between and in direct contact with the second sidewall and the fourth sidewall and between the organic interposer substrate and the first and the second semiconductor dies, wherein a top area of a portion of the first encapsulating layer between the second sidewall and the fourth sidewall is greater than a bottom area of the portion of first encapsulating layer;
• and
• forming a second encapsulating layer in contact with a top surface of the organic interposer substrate and surrounding the first and the second semiconductor dies, wherein the second encapsulating layer comprises a first portion in direct contact with the first sidewall and a second portion in direct contact with the third sidewall, and wherein each of the first portion and the second portion of the second encapsulating layer has a top width and a bottom width equal to the top width in a direction that is parallel to the top surface of the organic interposer substrate.