Semiconductor structure and manufacturing method thereof

A semiconductor structure comprising:

• a first die and a second die, wherein the first die has a first surface and a second surface opposite to the first surface, wherein the second die includes a sensor;
• a dielectric layer and an interconnect structure between the first die and the second die, wherein the first die and the second die are electrically connected by the interconnect structure, wherein the dielectric layer has a constant width, wherein the first surface of the first die is in contact with the dielectric layer, wherein the second die has a bottom surface in contact with the dielectric layer, wherein the dielectric layer is solid from an uppermost surface of the dielectric layer to a lowermost surface of the dielectric layer;
• a first molding in contact with a sidewall of the first die, wherein an entirety of the second surface of the first die is in contact with the first molding;
• and
• a second molding in contact with sidewalls of the second die,
• wherein a first portion of a top surface of the second die is covered by the second molding, and a second portion of the top surface of the second die is exposed through the second molding, wherein the second portion is aligned with the sensor of the second die.

A package comprising:

• a first semiconductor die, the first semiconductor die comprising a first insulating layer;
• a second semiconductor die, the second semiconductor die comprising a second insulating layer, wherein the second semiconductor die includes a sensor;
• a first redistribution structure between the first semiconductor die and the second semiconductor die, the first redistribution structure comprising conductive features that electrically couple the first semiconductor die to the second semiconductor die, the first redistribution structure contacting the first insulating layer of the first semiconductor die and the second insulating layer of the second semiconductor die, the first redistribution structure having a constant width, wherein the first redistribution structure is free of solder and underfill, wherein no active devices are positioned between a first surface of the first redistribution structure and a second surface of the first redistribution structure, the first surface of the first redistribution structure facing the first semiconductor die, the second surface of the first redistribution structure facing the second semiconductor die;
• a first encapsulant surrounding the first semiconductor die, the first encapsulant completely covering a first surface and sidewalls of the first semiconductor die, the first surface of the first semiconductor die facing away from the first redistribution structure;
• and
• a second encapsulant surrounding the second semiconductor die, wherein the second encapsulant only partially covers a lateral surface of the second semiconductor die, wherein a first portion of the lateral surface of the second semiconductor die is exposed through the second encapsulant, wherein the first portion is aligned over the sensor, the lateral surface of the second semiconductor die being opposite to the first redistribution structure.