Semiconductor structure, dicing method thereof, and memory

A method of dicing a semiconductor structure, comprising:

• providing a semiconductor structure to be diced,
• wherein the semiconductor structure to be diced comprises a first wafer, a second wafer, and a third wafer,
• wherein the first wafer comprises a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a pointing direction of the first mark is the same as an extending direction of the first dicing lane, and a cleavage plane of the first wafer is parallel to the pointing direction of the first mark,
• wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips,
• wherein the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer, and
• wherein the third wafer comprises a plurality of second peripheral circuit chips and a second mark at an edge of the third wafer, an included angle between a pointing direction of the second mark and an extending direction of a second dicing lane, between the second peripheral circuit chips, being α, where 0°<α<90°;
• dicing the first dicing lane from a side of the first wafer away from the second wafer;
• and
• stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer extends to the second wafer.

A method of forming a memory, comprising:

• providing a semiconductor structure to be diced,
• wherein the semiconductor structure to be diced comprises a first wafer, a second wafer, and a third wafer,
• wherein the first wafer comprises a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a pointing direction of the first mark is the same as an extending direction of the first dicing lane, and a cleavage plane of the first wafer is parallel to the pointing direction of the first mark,
• wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips,
• wherein the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer, and
• wherein the third wafer comprises a plurality of second peripheral circuit chips and a second mark at an edge of the third wafer, the second mark indicating a direction along a line of symmetry of the third wafer, and the line of symmetry of the third wafer being non-collinear with the line of symmetry of the first wafer;
• dicing the first dicing lane from a side of the first wafer away from the second wafer;
• and
• stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer extends to the second wafer.