Semiconductor device structure having a multi-layer conductive feature and method making the same

An interconnect structure, comprising:

• a source/drain contact disposed on a source/drain;
• a metal via disposed on the source/drain contact, wherein the metal via is disposed in a first plurality of dielectric layers of a via level of an interconnect structure, wherein the first plurality of dielectric layers has a first thickness along a first direction, the metal via has a first height along the first direction between a top of the metal via and a bottom of the metal via, and the first height is equal to the first thickness;
• and
• a metal line disposed on the metal via, wherein the metal line is disposed in a second plurality of dielectric layers of a metal line level of the interconnect structure, the second plurality of dielectric layers has a second thickness along the first direction, the source/drain contact, the metal via, and the metal line are sequentially stacked along the first direction, the metal line has a second height along the first direction between a top of the metal line and a bottom of the metal line, the second height is equal to the second thickness, the metal line has a first sidewall and a second sidewall that extend from the top of the metal line to the bottom of the metal line, the metal line has a width along a second direction between the first sidewall and the second sidewall, the second direction is different than the first direction, and the metal line includes:
• a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer forms a lower portion of the metal line having a third thickness along the first direction, the second metal layer and the third metal layer combine to form an upper portion of the metal line having a fourth thickness along the first direction, a sum of the third thickness and the fourth thickness is equal to the second height of the metal line, and the third thickness is greater than a fifth thickness of a bottom dielectric layer of the second plurality of dielectric layers, wherein the fifth thickness of the bottom dielectric layer of the second plurality of dielectric layers is less than the second thickness of the second plurality of dielectric layers,
• wherein the first metal layer extends the width of the metal line and forms a lower portion of the first sidewall of the metal line and a lower portion of the second sidewall of the metal line,
• the second metal layer extends the width of the metal line and forms an upper portion of the first sidewall of the metal line and an upper portion of the second sidewall of the metal line,
• wherein the first metal layer is between the metal via and the second metal layer and the first metal layer extends from a first sidewall of the second plurality of dielectric layers to a second sidewall of the second plurality of dielectric layers, and
• wherein the second metal layer is between the third metal layer and the first metal layer, the second metal layer is between the third metal layer and the second plurality of dielectric layers, and the second metal layer also extends from the first sidewall of the second plurality of dielectric layers to the second sidewall of the second plurality of dielectric layers.

A device structure comprising:

• a first etch stop layer having a first thickness, a first interlayer dielectric layer having a second thickness disposed on the first etch stop layer, a second etch stop layer having a third thickness disposed on the first interlayer dielectric layer, and a second interlayer dielectric layer having a fourth thickness disposed on the second etch stop layer, wherein the first etch stop layer, the first interlayer dielectric layer, the second etch stop layer, and the second interlayer dielectric layer are sequentially disposed over a substrate;
• a first interconnect structure that extends through the first interlayer dielectric layer and the first etch stop layer and is electrically connected to a conductive feature of a transistor, wherein the first interconnect structure has a fifth thickness that is the same as a sum of the first thickness of the first etch stop layer and the second thickness of the first interlayer dielectric layer, wherein the first thickness is less than the second thickness;
• and
• a second interconnect structure that extends through the second interlayer dielectric layer and the second etch stop layer to the first interconnect structure, wherein the second interconnect structure has a sixth thickness that is the same as a sum of the third thickness of the second etch stop layer and the fourth thickness of the second interlayer dielectric layer, wherein the third thickness is less than the fourth thickness, and wherein the second interconnect structure includes:
• a bottom layer having a seventh thickness disposed on the first interconnect structure, wherein sidewalls of the bottom layer interface with the second etch stop layer and the second interlayer dielectric layer, and
• a top portion having an eighth thickness disposed on the bottom layer, wherein the eighth thickness is greater than the seventh thickness, a sum of the seventh thickness and the eighth thickness is equal to the sixth thickness, and:
• the top portion includes a first top layer and a second top layer over the first top layer;
• a bottom of the first top layer interfaces with the bottom layer, sidewalls of the first top layer interface with the second interlayer dielectric layer, and a top of the first top layer interfaces with the second top layer;
• and
• the first top layer separates the second top layer from the bottom layer and the second interlayer dielectric layer.