Semiconductor device

A semiconductor device comprising:

• a first interlayer insulating layer;
• a lower wiring disposed inside the first interlayer insulating layer, the lower wiring comprising a filling layer and a barrier layer;
• an etching stop layer disposed on the first interlayer insulating layer, the etching stop layer comprising a first layer, a second layer, and a third layer;
• a second interlayer insulating layer disposed on the etching stop layer;
• and
• a via comprising a first portion disposed inside the first layer, a second portion disposed inside the second layer, a third portion disposed inside the third layer, and a fourth portion disposed inside the second interlayer insulating layer, the via comprising a first filling layer,
• wherein a width of the third portion in a horizontal direction is greater than a width of the first portion in the horizontal direction,
• wherein the width of the first portion in the horizontal direction is greater than a width of the second portion in the horizontal direction,
• wherein each of at least a part of an upper surface of the first portion and at least a part of a lower surface of the third portion is in contact with the second layer,
• wherein the via further comprises a first barrier layer comprising side portions on side walls of the first filling layer and a bottom portion on a bottom surface of the first filling layer, and
• wherein a portion of the first layer of the etching stop layer and the bottom portion of the first barrier layer contact the filling layer.

A semiconductor device comprising:

• a substrate;
• a first interlayer insulating layer disposed on the substrate;
• a lower wiring disposed inside the first interlayer insulating layer, the lower wiring comprising a filling layer and a barrier layer;
• an etching stop layer disposed on the first interlayer insulating layer, the etching stop layer comprising a first layer, a second layer, and a third layer, each of the first layer, the second layer, and the third layer comprising an aluminum compound,
• a second interlayer insulating layer disposed on the etching stop layer;
• a via penetrating the second interlayer insulating layer and the etching stop layer and being connected to the lower wiring, the via comprising a first portion disposed inside the first layer, a second portion disposed inside the second layer, a third portion disposed inside the third layer, a fourth portion disposed inside the second interlayer insulating layer, a first protrusion protruding in a horizontal direction from a level of a side wall of the second portion that contacts the second layer toward the first layer, and a second protrusion protruding in the horizontal direction from the level of a side wall of the second portion that contacts the second layer toward the third layer, the via comprising a first filling layer;
• and
• an upper wiring disposed on the via and connected to the via, a width of the upper wiring in the horizontal direction being greater than a width of the via in the horizontal direction,
• wherein a first length of the first protrusion in the horizontal direction is smaller than a second length of the second protrusion in the horizontal direction,
• wherein each of an upper surface of the first protrusion and a lower surface of the second protrusion is in contact with the second layer,
• wherein an upper surface of the second protrusion is in contact with the second interlayer insulating layer,
• wherein the via further comprises a first barrier layer comprising side portions on side walls of the first filling layer and a bottom portion on a bottom surface of the first filling layer, and
• wherein a portion of the first layer of the etching stop layer and the bottom portion of the first barrier layer contact the filling layer.